Objectives, Introduction, Language Models, Abstract Models, Compilation and Behavioral Optimization, Solved Problems, Review Questions.
4. Architectural Synthesis and Algorithm
Objectives, Introduction, The Design Space, Resources and Constraints, Resources, Constraints, Scheduling and Binding, The Temporal Domain: Scheduling, The Spatial Domain: Binding, Hierarchical Models, Area and Performance Estimation, The Synchronization Problem, The Model, Scheduling without Resource Constraints, Scheduling under Timing Constraints, Relative Scheduling, Scheduling under Resource Constraint, Scheduling in Pipelined Circuits, Solved Problems, Review Questions.
5. Resource Sharing and Optimization
Objectives, Introduction, Sharing and Binding for Resource-dominated Circuits, Non-Hierachical Sequencing Graph, Hierachical Sequencing Graph, Register Sharing, Bus Sharing and Binding, Introduction to Logic Optimization, Logic Optimization Principles, Definitions, Algorithms for Exact Logic Minimization, Heuristic Logic Minimization, Testability, Operations on Two-Level Logic Covers, Positional-Cube Notation of Binary-Valued Functions, Positional-Cube Notation of Multiple-Valued Functions, Unate Functions and Unate Covers, The Unate Recursive Paradigm, Review Questions.
6. Floorplanning, Placement and Routing
Objectives, Floorplanning, Floorplanning Goals and Objectives, Channel Definition, I/O and Power Planning, Clock Planning, Placement, Goals, Measurement of Placement Objectives, Placement Algorithms, Simulated Annealing, Time-Driven Placement, Global Routing, Goals and Objectives, Global Routing Methods, Global Routing Between Blocks, Detailed Routing, Goals and Objectives, Left–Edge Algorithm, Constraints and Routing Graphs, Clock Routing, Power Routing, Design Checks, Via Minimization, Review Questions.